1. Field of the Invention
The present invention relates to a method of rounding the corner of shallow trench isolation region, more particularly to a chemical method of rounding the corner of the shallow trench isolation region.
2. Description of the Prior Art
Recently, as the manufacturing techniques of semiconductor integrated circuits develop, the number of elements in a chip increases. The size of the element decreases as the degree of integration increases. The line width used in manufacturing lines has decreased from sub-micron to quarter-micron, or even to a smaller size. However regardless of the reduction of the size of the element, adequate insulation or isolation must be formed among individual elements in the chip so that good element characteristics can be achieved. This technique is called device isolation technology. The main object is to form an isolation region, and reduce the size of the isolation to as small as possible while assuring good isolation effect to have larger chip space for more elements.
Among different element isolation techniques, LOCOS and shallow trench isolation region manufacturing methods are the two most used methods. In particular, as the latter has the small isolation region and can maintain the substrate to be level after the process is finished, it is the semiconductor manufacturing method obtaining the most attention.
The conventional manufacturing method for shallow trench isolation region is shown in the cross sectional views of FIGS. 1A to 1D.
Refer to FIG. 1A. A pad oxide layer 12 is formed on a silicon substrate 10 using thermal oxidation and a silicon nitride layer 14 is deposited on the pad oxide layer 12 using the CVD method. Next, a photoresist layer 16 is coated on the silicon nitride layer 14 and is patterned using photolithography to expose the portion where the element isolation region is to be formed. Silicon nitride layer 14 and pad oxide layer 12 are etched sequentially using the photoresist layer 16 as a mask.
Next, refer to FIG. 1B, after photoresist layer 16 is removed with adequate liquid, silicon nitride layer 14 and pad oxide layer 12 are used as a mask to etch silicon substrate 10 to form trench 20 inside to define the active region of the element. Subsequently, thermal oxidation is performed to grow a thin silicon oxide layer as the lining oxide layer 24 on the bottom and sidewall of the trench 20. However, when silicon oxide is formed, the stress is concentrated on the curvature region of a smaller radius, and the corner 22 of trench 20 is a sharp curvature of small radius, the growing speed of the silicon oxide at the corner 22 of the trench 20 is slower, so that the lining oxide layer 24 at the corner 22 of the trench 20 is very thin.
Next, chemical vapor deposition is performed, for example using O3 and TEOS as a reactant to form oxide layer 26, and fill the trench 20 and cover the surface of the silicon nitride layer 14.
Next, refer to FIG. 1C. A chemical mechanical polishing process is performed, the part of oxide layer 26 that is higher than the surface of the silicon nitride layer 14 is removed to form the isolation region 26a with a level surface. Subsequently, a suitable etching method is used to remove the silicon nitride layer 14 and pad oxide layer 12 in order to complete the manufacturing of the shallow trench isolation, and obtain the structure shown in FIG. 1D.
Because the property of the element isolation region 26a is similar to that of the pad oxide layer 12, when etching liquid is used to dip pad oxide layer 12, the element isolation region 26a is inevitably etched so that the corner 22 of the trench 20 is exposed and an indentation 30 is formed next to the corner 22 of the trench 20.
Thus, when the gate oxide layer and gate conductive layer are formed later, the conductive layer deposited in the indentation 30 is not easy to remove and a short circuit between the adjacent transistors is easily formed. In addition, since the gate oxide layer at the corner 22 of the trench 20 is thinner than other places, a parasitic transistor is formed. This phenomenon is equivalent to two transistors with gate oxide layers of different thickness in parallel. When current goes through this parasitic transistor, as the curvature radius of the corner 22 of the trench 20 is small, the electric fields concentrate and the Fowler-Nordheim current increases, hence the insulating property of the gate oxide layer of the corner 22 degrades, resulting in abnormal element characteristics. For example, there is a kink effect in I-V curvature of Id and Vg, which generates a double hump.
From the above, the present invention provides a method of increasing the curvature radius of the corner of the trench.
Furthermore, the present invention provides a manufacturing method, which avoids forming a trench isolation region of parasitic transistors at the corner of the trench.
Furthermore, the present invention provides a manufacturing method of forming a trench isolation region, which avoids the short circuit that occurs between adjacent transistors.
Therefore, the present invention provides a method of rounding the corner of the shallow trench isolation region, the method includes: forming a pad oxide layer and mask layer sequentially on silicon substrate and patterning them, and then using the patterned pad oxide layer and mask layer as the etching mask to etch the silicon substrate and form the trench in the silicon substrate; next, use the oxidizing agent and HF liquid in turn to round the trench corner, subsequently remove part of the mask layer to expose the rounded corner of the trench, then forming an oxide layer to fill the trench, finally removing the mask layer and the pad oxide layer to form a trench isolation region.
According to one preferred embodiment of the present invention, the concentration of the HF liquid is about 0.3% to 2%. Oxidizing agents include H2O2(aq) and HNO3(aq). The concentration of the H2O2(aq) is about 5% to 20%; the concentration of the HNO3(aq) is about 3% to 30%. In the process of alternating use of the oxidizing agent and HF liquid, a de-ionizing water process, after the oxidizing agent and HF liquid process, is included.
The present invention provides a method of rounding the corner of the shallow trench isolation region, which includes the following steps: forming a pad oxide layer and a mask layer sequentially on a silicon substrate, and patterning them, then using patterned pad oxide layers and mask layers as etching masks to etch the silicon substrate and form a trench in the silicon substrate; next, after part of the pad oxide layer is removed, the surface of the silicon substrate in the trench is oxidized to form silicon dioxide, then part of pad oxide layer and silicon dioxide of the surface of the silicon substrate in the trench is removed, and repeating the step of oxidizing the surface of the silicon substrate and the step of removing part of the pad oxide layer and silicon dioxide until the corner of the trench is rounded, then part of the mask layer is removed to expose the rounded corner of the trench, to form an oxide layer, filling the trench, finally removing the mask layer and the pad oxide layer to form the trench isolation region.
According to a preferred embodiment of the present invention, the method of oxidizing the silicon substrate includes using an oxidizing agent, this oxidizing agent includes H2O2(aq) and HNO3(aq), after using this oxidizing agent, the method further includes a de-ionizing water process. The method of removing part of the pad oxide layer and silicon dioxide includes using HF liquid, after using this HF liquid, the method further includes a de-ionizing water process.